FIG. 1 shows a block diagram of a portion of a conventional system-on-chip (SOC) 100, such as a digital signal processor (DSP). As shown, the SOC includes a processor 110 coupled to a memory module 160 via a bus 180. The memory module stores a computer program comprising a sequence of instructions. During operation of the SOC, the processor retrieves and executes the computer instructions from memory to perform the desired function.
SOCs can be provided with multiple processors. However, conventional memory modules are only capable of being accessed by one processor at a time. Thus, if memory is busy (i.e., accessed by another processor for program execution), a processor which desires to access the busy memory module must wait and remain idle until the memory is available upon completion of program execution. This can severely hinder system performance since a processor must remain idle for the duration of program execution. To avoid performance degradation in multi-processor SOCs caused by memory conflicts, each processor is associated with its own memory module. However, providing duplicate memory modules increases the size of the chip, which undesirably hinders miniaturization as well as increases cost of manufacturing.
As evidenced from the above discussion, it is desirable to provide a system in which the processors can share a memory module to reduce chip size without incurring the performance penalty of conventional designs.